As semiconductor memory devices capable of storing mass data for use, variable resistance memories (ReRAM: Resistance Random Access Memory) and so forth, which can be easily formed in three dimensions, have received attention. Cells of these variable resistance memories are characterized in the asymmetry of the voltage-current characteristic that greatly changes in accordance with the polarity of the voltage applied to the memory cell.
Conventionally, the semiconductor memory device including the variable resistance memory cells distinguishes a selection-targeted memory cell (hereinafter referred to as a “selected memory cell”) from other memory cells (hereinafter referred to as “non-selected memory cells”) by applying a bias, different from that to the selected memory cell, to all non-selected memory cells from external to make access to the selected memory cell. In accordance with setting of the bias, it is possible to increase the margin of failed operation of non-selected memory cells, thereby ensuring reliable operation of the cell array. The setting of the bias is not easy, however, and when it is intended to make access under an optimal bias condition, an increase occurs in current consumption, for example, as a problem.
Therefore, when these variable resistance memories are used in mass storage semiconductor memory devices, the size of the access-target cell array cannot be increased sufficiently. As a result, the share of memory cells in a semiconductor memory device lowers and the merit of the three-dimensional structure cannot be exerted sufficiently.    [Patent Document 1] JP 2010-33675A